EDN

How to Read Data Sheets: Logic Timing (Part 3, Flip-Flops)

The JK flip-flop augments the behavior of the SR flip-flop (J = Set, K = Reset) by interpreting the J = K = 1 condition as a “flip” or toggle command. In my previous column, we introduced latches and ...
Electronic Design

Make A Dual ECL Latch Function As A Dual R-S Flip-Flop

The MC1030 is a clocked dual D-type latch. Any change in the D input will be reflected at the output while the clock is low. The outputs are latched on the clock's ...
Hackaday

sr latch

With a 555 on the BOM, you never know what you’re going to get. With 40 of the versatile timer chips in a build, you might just get something completely unexpected, like this 555-based eight-bit ...
Design-Reuse

Latches and timing closure: a mixed bag

Digital blocks contain combinational and sequential circuits. Sequential circuits are the storage cells with outputs that reflect the past sequence of their input values, while output of the ...
Hackaday

Learning Verilog For FPGAs: Flip Flops

Last time I talked about how to create an adder in Verilog with an eye to putting it into a Lattice iCEstick board. The adder is a combinatorial circuit and didn’t use a clock. This time, we’ll finish ...